1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly a semiconductor device manufactured by using a phase shift mask to control current characteristics and a manufacturing method thereof.
2. Description of the Related Art
As miniaturization of a semiconductor device advances, it is becoming difficult to suppress a variation in feature sizes. In particular, a variation in a patterned gate electrode size of a metal-insulator-semiconductor field-effect transistor (MISFET) is one of the causes of a variation in electrical characteristics, e.g., a current driving force of the MISFET. In order to suppress this variation, improvement in, e.g., a resolution and/or depth of focus (DOF) of lithography, is demanded.
One of methods of improving performance of lithography is a method of using a phase shift mask, e.g., a Levenson mask (an alternating-phase shift mask). In the Levenson mask, usually, a phase of light transmitted through a pair of opening portions adjacent to each other is shifted 180°, namely, a phase is inverted each other, to improve a critical resolution or a depth of focus. The phase inverted pattern arrangement is called a Levenson arrangement, in which the phases are expressed by using 0 and π.
However, in an actual pattern of the Levenson mask used in manufacturing a semiconductor device, patterns adjacent to each other do not have a desired Levenson arrangement, e.g., an arrangement of 0, π, 0, π, but has an arrangement of an inversed phase, i.e., π, 0, π, 0, . . . , in some cases. Jpn. Pat. Appln. KOKAI Publication No. 2000-77531 discloses a semiconductor device, which has both patterns of isolated patterns and line-and-space patterns, manufactured by using a mask pattern having the Levenson arrangement. In this technology, a pair of the two patterns is determined as one active region, and the active regions adjacent to each other are arranged in staggered manner, thereby realizing a mask pattern of the Levenson arrangement.
When using the Levenson mask in gate electrode patterning, it is general to invert a phase of light to 0 and π or to π and 0 on a source side and a drain side of a gate electrode. FIGS. 12A to 12D are views showing examples of correlation of a layout pattern and a Levenson mask pattern arrangements of each MISFET. In the figures, the layout pattern of the gate electrode G is shown by a pattern with solid oblique lines and the Levenson mask patterns Sm and Dm are shown by patterns with broken oblique lines. Referring to FIG. 12A, an example where two MISFETs are vertically arranged will now be considered. In one MISFET, a source S is provided on a left-hand side of the gate electrode G and a drain D is provided on a right-hand side to interpose the gate electrode G therebetween. The gate electrodes G of the two MISFETs are connected with each other through a contact region. A Levenson mask pattern is generally generated automatically by means of computer aided design (CAD) with respect to such a layout pattern. At that time, although processing is carried out in such a manner that a source region (Sm) and a drain region (Dm) of the mask do not have the same phase, one of four combination patterns of 0 and π regions such as shown in FIGS. 12A to 12D is generated. That is, in the pattern to be automatically generated, a phase may vary depending on surrounding layout patterns, and one desired pattern, which is any one of the four illustrated patterns, cannot be always generated in a given region.
Although the Levenson mask improves a resolution and DOF of lithography, slight variation in a light transmittance of a 0 region and a π region of the mask is caused by a phase shifting processing of the mask. Therefore, the Levenson mask patterns depicted in FIGS. 12A to 12D cannot guarantee that the gate electrodes having completely the same shapes are always patterned. FIGS. 13A and 13B are views for explaining such example. FIG. 13A is a view showing an arrangement of gate electrodes and a Levenson mask pattern, and a π region and a 0 region are alternately arranged from the left side to right side with respect to three gate electrodes. FIG. 13B is a view showing shape of gate patterns after patterning the gate electrodes G by using this Levenson mask. As apparent from the drawing, the gate electrode may be patterned into a shape like a bulging rod in such a manner that it bulges from the 0 region toward the π region. Such an example is disclosed in “A Novel Robust Optimization Method of Exposure and Mask Conditions for beyond 65 nm-node Lithography” by K. Takeuchi et. al., Proc. of SPIE, Vol. 5853, pp. 265-276, (2005).